A 200 millimetre silicon wafer in a lithography scanner during manufacture at the X-Fab Silicon Foundries SE semiconductor plant in Corbeil-Essonnes, France, on June 1. Thinner wafers with stacked integrated circuits could be key to unlocking next-generation chip technology. Photo: Bloomberg
A 200 millimetre silicon wafer in a lithography scanner during manufacture at the X-Fab Silicon Foundries SE semiconductor plant in Corbeil-Essonnes, France, on June 1. Thinner wafers with stacked integrated circuits could be key to unlocking next-generation chip technology. Photo: Bloomberg

Next-gen chip tech could be unlocked with 3D packaging tools from 80-year-old Japanese company

  • Japanese toolmaker Disco is betting on 3D packaging for chips by stacking integrated circuits on silicon wafers of near-transparent thinness
  • As Moore’s Law nears its physical limits, chip makers are looking at new materials and designs to get better performance out of next-generation hardware

Topic |   Semiconductors
A 200 millimetre silicon wafer in a lithography scanner during manufacture at the X-Fab Silicon Foundries SE semiconductor plant in Corbeil-Essonnes, France, on June 1. Thinner wafers with stacked integrated circuits could be key to unlocking next-generation chip technology. Photo: Bloomberg
A 200 millimetre silicon wafer in a lithography scanner during manufacture at the X-Fab Silicon Foundries SE semiconductor plant in Corbeil-Essonnes, France, on June 1. Thinner wafers with stacked integrated circuits could be key to unlocking next-generation chip technology. Photo: Bloomberg
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